Field
Aspects of the present disclosure relate generally to integrated circuits, and more particularly, to a method and apparatus for routing die signals using external interconnects.
Background
Effective routing of various signals in modern integrated circuits involves overcoming many challenges, including ensuring proper timing of signal distribution, minimizing cross-talk, and matching impedances, all while complying with ever-shrinking available real estate due to higher component counts. The routing of clock signals is especially critical as these signals are used to synchronize different data signals arriving from different parts of the integrated circuit. However, due to impedances present in interconnects, there are often mismatches in clock signal arrival times at various locations of the integrated circuit because of varying spatial distances between a clock source and locations of circuits coupled to the clock source. These mismatches in timing are known as clock skews. Also, due to noise caused by other interconnect lines, such as those running in parallel with the clock signal lines, clock signals arriving at two different locations with the same clock input may also experience a phase noise, commonly known as clock jitter.
A clock distribution network (CDNs) may be used in an attempt to ensure constraints regarding clock skew and jitter are minimized. Other considerations such as fast transition times and a balanced duty cycle also need to be taken into account. CDNs may be designed using such different techniques as H-trees, buffered clock trees, balanced clock trees, and meshed clock networks. However, because interconnects do not scale proportionally to rapidly scaling transistor feature sizes that operate at high clock frequencies, the task of designing efficient CDNs is becoming even more difficult, even when using these techniques. For example, use of clock tree balancing alone is increasingly insufficient because clock buffer mismatches due to in-die process variations limit the ability to minimize skew. Also, traditional H-trees are not well-suited to distributing clocks to asymmetric, irregularly shaped clock domains, and even add further complication to the floor planning and layout of integrated circuits. Further, skew reduction techniques for existing H-tree distributions suffer from high power consumption and inefficient use of interconnects. Other approaches perform skew compensation at a source, independently for each leaf. However, these approaches require long and varying lengths of reference lines returning from each leaf to the source, which introduces errors to skew compensation because of a process-dependent delay of each feedback line. In addition, CDN design must often be finalized before the design of the rest of the circuits in the integrated circuit may be completed, because the level of difficulty in designing efficient CDNs increases in the latter stages of design.
Differential signaling is another approach that may be used to distribute clock signals. Although differential signaling is more effective in many ways as compared to a clock tree approach, implementation of this technique requires more real estate to support the relatively complex circuits that are needed to provide differential signaling. Also, careful routing is required to ensure low resistance of the differential signals over long distances, which often consumes valuable routing resources as higher layers are often used to achieve this requirement. Still another consideration is that the differential signaling circuits require shielding, and provisions that therefor further reduce the desirability of the approach.
As clock distribution for modern integrated circuits becomes more difficult to implement because of increasingly complex systems, decreased power supply voltages, larger die sizes, and higher clock rates, the desirability to be able to overcome the challenges described also becomes more apparent.